ANALYTICAL MODELING OF COST EFFICIENT QUAD MATERIAL GATE ALL AROUND STACK ARCHITECTURE OF TUNNEL FET.

JOURNAL ARTICLE published 28 February 2017 in International Journal of Advanced Research

Authors: G. Poshamallu | Assistant professor , Department Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana. | G.Siri Chandana | S.Sai Abhinav. | IV BTECH, Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana. | IV BTECH, Department Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Cheeryal (V), Keesara Mandal, Ranga Reddy Dist.-501301, Telangana..