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A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation

JOURNAL ARTICLE published December 2004 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: G. Braun | A. Nohl | A. Hoffmann | O. Schliebusch | R. Leupers | H. Meyr

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

JOURNAL ARTICLE published April 2004 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Constrained Floorplanning Using Network Flows

JOURNAL ARTICLE published April 2004 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: Y. Feng | D.P. Mehta | H. Yang

Repeater Scaling and Its Impact on CAD

JOURNAL ARTICLE published April 2004 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: P. Saxena | N. Menezes | P. Cocchini | D.A. Kirkpatrick

PartGen: a generator of very large circuits to benchmark the partitioning of FPGAs

JOURNAL ARTICLE published 2000 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: J. Pistorius | E. Legai | M. Minoux

Physically Rigorous Modeling of Internal Laser-Probing Techniques for Microstructured Semiconductor Devices

JOURNAL ARTICLE published January 2004 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: R.K. Thalhammer | G.K.M. Wachutka

Robust VLSI circuit simulation techniques based on overlapped waveform relaxation

JOURNAL ARTICLE published April 1995 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M.E. Mokari | D. Smart

Modeling digital substrate noise injection in mixed-signal IC's

JOURNAL ARTICLE published March 1999 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: E. Charbon | P. Miliozzi | L.P. Carloni | A. Ferrari | A. Sangiovanni-Vincentelli

Applying simulated evolution to high level synthesis

JOURNAL ARTICLE published March 1993 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: T.A. Ly | J.T. Mowchenko

Channel density reduction by routing over the cells

JOURNAL ARTICLE published August 1991 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Accelerating Markovian analysis of asynchronous systems using state compression

JOURNAL ARTICLE published July 1999 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: P.A. Beerel

RP-SYN: synthesis of random pattern testable circuits with test point insertion

JOURNAL ARTICLE published 1999 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: N.A. Touba | E.J. McCluskey

Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

JOURNAL ARTICLE published 2000 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: S.J.E. Wilton

Graph based analysis of 2-D FPGA routing

JOURNAL ARTICLE published January 1996 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: S. Tsukiyama | M. Marek-Sadowska

An efficient method for generating exhaustive test sets

JOURNAL ARTICLE published 1995 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: R.T. Stanion | D. Bhattacharya | C. Sechen

Exploiting communication complexity for Boolean matching

JOURNAL ARTICLE published 1996 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

JOURNAL ARTICLE published 2000 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: P. Tafertshofer | A. Ganz | K.J. Antreich

Computing the area versus delay trade-off curves in technology mapping

JOURNAL ARTICLE published 1995 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: K. Chaudhary | M. Pedram

PLADE: a two-stage PLA decomposition

JOURNAL ARTICLE published 1992 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M.J. Ciesielski | S. Yang

Congestion minimization during placement

JOURNAL ARTICLE published 2000 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M. Sarrafzadeh