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Hierarchical VLSI Routing--An Approximate Routing Procedure

JOURNAL ARTICLE published April 1985 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: A.M. Patel | N.L. Soong | R.K. Korn

A Simulation Model for Schottky Diodes in GaAs Integrated Circuits

JOURNAL ARTICLE published April 1983 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: D.B. Estreich

An Approach to Solving Multiparticle Diffusion Exhibiting Nonlinear Stiff Coupling

JOURNAL ARTICLE published October 1985 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: H.R. Yeager | R.W. Dutton

McBOOLE: A New Procedure for Exact Logic Minimization

JOURNAL ARTICLE published January 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M.R. Dagenais | V.K. Agarwal | N.C. Rumin

The Role of Semiconductor Device Diameter and Energy-Band Bending in Convergence of Picard Iteration for Gummel's Map

JOURNAL ARTICLE published October 1985 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: J.W. Jerome

Stochastic Models for Wireability Analysis of Gate Arrays

JOURNAL ARTICLE published January 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: S. Sastry | A.C. Parker

A Fast-Timing Simulator for Digital MOS Circuits

JOURNAL ARTICLE published October 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: D. Tsao

Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

JOURNAL ARTICLE published January 1983 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: R.H. Krambeck | H.-F.S. Law | A.D. Lopez

Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions

JOURNAL ARTICLE published January 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: W. Kuzmicz

Methodology Verification of Hierarchically Described VLSI Circuits

JOURNAL ARTICLE published January 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: I.L. Bain | L.A. Glasser

Current Lines and Accurate Contact Current Evaluation in 2-D Numerical Simulation of Semiconductor Devices

JOURNAL ARTICLE published October 1985 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: E. Palm | F. Van de Wiele

Topological Optimization of Multiple-Level Array Logic

JOURNAL ARTICLE published November 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: S. Devadas | A.R. Newton

SPIDER -- A CAD System for Modeling VLSI Metallization Patterns

JOURNAL ARTICLE published November 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: J.E. Hall | D.E. Hocevar | M.J. McGraw

Pad Assignment for Power Nets in VLSI Circuits

JOURNAL ARTICLE published July 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M. Marek-Sadowska

An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess

JOURNAL ARTICLE published January 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: R.W. Dutton | M. Vanzi

A Predictor/CAD Model for Buried-Channel MOS Transistors

JOURNAL ARTICLE published January 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: K.C.-K. Weng

Layering Algorithms For Single-Row Routing

JOURNAL ARTICLE published January 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: S. Sahni

A Meyer-Like Approach for the Transient Analysis of Digital MOS IC's

JOURNAL ARTICLE published October 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: C. Turchetti | P. Prioretti | G. Masetti | E. Profumo | M. Vanzi

A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

JOURNAL ARTICLE published January 1983 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: L.J. Hafer | A.C. Parker

Models for a New Profit-Based Methodology for Statistical Design of Integrated Circuits

JOURNAL ARTICLE published January 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: D. Riley | A. Sangiovanni-Vincentelli