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Generalization of Yield Optimization Problem: Maximum Income Approach

JOURNAL ARTICLE published April 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: L.J. Opalski | M.A. Styblinski

A Hierarchical Standard Cell Approach for Custom VLSI Design

JOURNAL ARTICLE published July 1984 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: T. Tokuda | J. Korematsu | O. Tomisawa | S. Asai | I. Ohkura | T. Enomoto

PART: Programmable Array Testing Based on a Partitioning Algorithm

JOURNAL ARTICLE published April 1984 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: F. Somenzi | M. Mezzalama | P. Prinetto

Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits

JOURNAL ARTICLE published October 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M.R. Mercer

Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions

JOURNAL ARTICLE published January 1986 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: W. Kuzmicz

Bipartite Folding and Partitioning of a PLA

JOURNAL ARTICLE published July 1984 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: J.R. Egan | C.L. Liu

A Ranking Algorithm for MOS Circuit Layouts

JOURNAL ARTICLE published January 1987 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: C.A. Neff | R. Nair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

JOURNAL ARTICLE published August 2008 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

JOURNAL ARTICLE published December 2008 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: David Walter | Scott Little | Chris Myers | Nicholas Seegmiller | Tomohiro Yoneda

Fast and Accurate Statistical Criticality Computation Under Process Variations

JOURNAL ARTICLE published March 2009 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: H.D. Mogal | H. Qian | S.S. Sapatnekar | K. Bazargan

Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear Periodic Circuits

JOURNAL ARTICLE published March 2009 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: A. Brambilla | G. Gruosso | G.S. Gajani

Table of contents

JOURNAL ARTICLE published April 2009 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE 2009 Membership Application

JOURNAL ARTICLE published April 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2010 IEEE International Symposium on Circuits and Systems (ISCAS2010)

JOURNAL ARTICLE published February 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Layout Generator for Transistor-Level High-Density Regular Circuits

JOURNAL ARTICLE published February 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: M. Marek-Sadowska | W.P. Maly

IEEE Embedded Systems Letters

JOURNAL ARTICLE published May 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Why we joined ... [advertisement]

JOURNAL ARTICLE published February 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SPARE—A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction

JOURNAL ARTICLE published June 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: Jorge Fernández Villena | Luís Miguel Silveira

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

JOURNAL ARTICLE published March 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data

JOURNAL ARTICLE published March 2010 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Authors: Nilanjan Mukherjee | Artur Pogiel | Janusz Rajski | Jerzy Tyszer