An Efficient Ic On chip Test Framework To Embed Tsv Testing In Memory Bist Using Dynamic Technique

JOURNAL ARTICLE published 26 December 2017 in International Journal of Business Intelligent

Authors: G.Vithya Ms | ME-VLSI Design, ,Sri Ramanujar Engineering,College, Vandalur, Kolappakkam,Chennai | P. Krishnakumar Mr | Assistant Professor (OG), ,Dept of ECE, Sri Ramanujar Engineering College,Vandalur,Kolappakkam, Chennai