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High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation

Journal Article published 15 Jun 2016 in International Journal of Computing Algorithm volume 5 issue 1 on pages 55 to 58

Authors: K. Neelaveni, Student, ME-VLSI Design, ,Sri Ramanujar Engineering College, Vandalur, Kolappakkam,Chennai, G. Saravanakumar, Assistant Professor (OG), ,Dept of ECE,Sri Ramanujar Engineering College,Vandalur,Kolappakkam, Chennai