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OpenCL Performance on the Intel Heterogeneous Architecture Research Platform

PROCEEDINGS ARTICLE published 22 September 2020 in 2020 IEEE High Performance Extreme Computing Conference (HPEC)

Research funded by NSF (CNS-1763503,CNS-1814739)

Authors: Steven Harris | Roger D. Chamberlain | Christopher Gill

https://doi.org/10.1109/hpec43674.2020.9286213 Actions

Interrupt management in protected mode operation of Intel 80286 high performance architecture

PROCEEDINGS ARTICLE published May 2012 in 2012 International Conference on Informatics, Electronics & Vision (ICIEV)

Authors: Golam Mostafa

https://doi.org/10.1109/iciev.2012.6317362 Actions

Xeon Phi Core Microarchitecture

BOOK CHAPTER published 2013 in Intel® Xeon Phi™ Coprocessor Architecture and Tools

Authors: Rezaur Rahman

https://doi.org/10.1007/978-1-4302-5927-5_4 Actions

HighPerformance Physical Simulations on NextGeneration Architecture with Many Cores

JOURNAL ARTICLE published 22 August 2007 in Intel Technology Journal

Authors: Yen-Kuang Chen

https://doi.org/10.1535/itj.1103.08 Actions

Organization, Segregation and Object Recognition

JOURNAL ARTICLE published 1999 in Intellectica. Revue de l'Association pour la Recherche Cognitive

Authors: Mary A. Peterson

https://doi.org/10.3406/intel.1999.1772 Actions

Optimization of RAID Erasure Coding Algorithms for Intel Xeon Phi

PROCEEDINGS ARTICLE published August 2016 in 2016 IEEE International Conference on Networking, Architecture and Storage (NAS)

Authors: Aleksei Marov | Andrey Fedorov

https://doi.org/10.1109/nas.2016.7549411 Actions

Accelerating Mobile Multimedia with Intel Wireless MMX™ Technology

PROCEEDINGS ARTICLE published in IEEE Sixth International Symposium on Multimedia Software Engineering

Authors: N.C. Paver | M.H. Khan | B.C. Aldrich

https://doi.org/10.1109/mmse.2004.20 Actions

Integrated Access Device (IAD) Solution Using Intel IXP2350 Network Processor

PROCEEDINGS ARTICLE published in Second International Conference on Embedded Software and Systems (ICESS'05)

Authors: Liu Naiqi Chen Yan

https://doi.org/10.1109/icess.2005.65 Actions

Revolutionizing validation: The Intel approach for TTM

PROCEEDINGS ARTICLE published December 2015 in 2015 10th International Design & Test Symposium (IDT)

Authors: Ra'ed Al-Omari | Shahil Rais

https://doi.org/10.1109/idt.2015.7396728 Actions

Architecture cognitive et comportements

JOURNAL ARTICLE published 2019 in Intellectica. Revue de l'Association pour la Recherche Cognitive

Authors: Bryan Fruchart | Benoît Leblanc

https://doi.org/10.3406/intel.2019.1924 Actions

Hardening Intel SGX Applications

PROCEEDINGS ARTICLE published 28 October 2017 in Proceedings of the 2nd Workshop on System Software for Trusted Execution

Authors: Kobe Vrancken | Frank Piessens | Raoul Strackx

https://doi.org/10.1145/3152701.3152711 Actions

A parallel algorithm of Euclidean distance matrix computation for the Intel Xeon Phi Knights Landing many-core processor

JOURNAL ARTICLE published August 2018 in Bulletin of the South Ural State University. Series "Computational Mathematics and Software Engineering"

https://doi.org/10.14529/cmse180305 Actions

Logique et dynamique des attitudes

JOURNAL ARTICLE published 1999 in Intellectica. Revue de l'Association pour la Recherche Cognitive

Authors: Philippe Robert-Demontrond

https://doi.org/10.3406/intel.1999.1588 Actions

Characterizing and optimizing Java-based HPC applications on Intel many-core architecture

JOURNAL ARTICLE published December 2017 in Science China Information Sciences

Authors: Yang Yu | Tianyang Lei | Haibo Chen | Binyu Zang

https://doi.org/10.1007/s11432-015-0989-3 Actions

The Efficiency of Hydrodynamic Code on Intel Xeon Scalable Architecture

PROCEEDINGS ARTICLE published September 2021 in 2021 Ivannikov Memorial Workshop (IVMEM)

Authors: Igor Kulikov | Igor Chernykh | Dmitry Karavaev | Anna Sapetina | Sergey Lomakin

https://doi.org/10.1109/ivmem53963.2021.00013 Actions

Xeon Phi Cache and Memory Subsystem

BOOK CHAPTER published 2013 in Intel® Xeon Phi™ Coprocessor Architecture and Tools

Authors: Rezaur Rahman

https://doi.org/10.1007/978-1-4302-5927-5_5 Actions

Development of a 16-bit microprocessor learning system using Intel 8086 architecture

PROCEEDINGS ARTICLE published December 2013 in 2013 2nd International Conference on Advances in Electrical Engineering (ICAEE)

Authors: Golam Mostafa

https://doi.org/10.1109/icaee.2013.6750323 Actions

Efficient, compact 2-phase power supply delivers 40A to Intel mobile CPUs

BOOK CHAPTER published 2015 in Analog Circuit Design

Authors: David Chen

https://doi.org/10.1016/b978-0-12-800001-4.00012-0 Actions

Xeon Phi Application Development Tools

BOOK CHAPTER published 2013 in Intel® Xeon Phi™ Coprocessor Architecture and Tools

Authors: Rezaur Rahman

https://doi.org/10.1007/978-1-4302-5927-5_8 Actions

Staggered Dslash Performance on Intel Xeon Phi Architecture

PROCEEDINGS ARTICLE published 21 May 2015 in Proceedings of The 32nd International Symposium on Lattice Field Theory — PoS(LATTICE2014)

Authors: Ruizi Li | Steven Gottlieb

https://doi.org/10.22323/1.214.0034 Actions
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