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Overview of Deep Neural Networks

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_2 Actions

Efficient Processing of Deep Neural Networks

BOOK published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7 Actions

Conclusion

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_11 Actions

Introduction

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_1 Actions

Designing Efficient DNN Models

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_9 Actions

Reducing Precision

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_7 Actions

Kernel Computation

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_4 Actions

Advanced Technologies

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_10 Actions

Exploiting Sparsity

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_8 Actions

Designing DNN Accelerators

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_5 Actions

Operation Mapping on Specialized Hardware

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_6 Actions

Efficient Processing of Deep Neural Networks

JOURNAL ARTICLE published 16 June 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.2200/s01004ed1v01y202004cac050 Actions

Key Metrics and Design Objectives

BOOK CHAPTER published 2020 in Synthesis Lectures on Computer Architecture

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1007/978-3-031-01766-7_3 Actions

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

JOURNAL ARTICLE published December 2017 in Proceedings of the IEEE

Authors: Vivienne Sze | Yu-Hsin Chen | Tien-Ju Yang | Joel S. Emer

https://doi.org/10.1109/jproc.2017.2761740 Actions

14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

PROCEEDINGS ARTICLE published January 2016 in 2016 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Yu-Hsin Chen | Tushar Krishna | Joel Emer | Vivienne Sze

https://doi.org/10.1109/isscc.2016.7418007 Actions

A method to estimate the energy consumption of deep neural networks

PROCEEDINGS ARTICLE published October 2017 in 2017 51st Asilomar Conference on Signals, Systems, and Computers

Authors: Tien-Ju Yang | Yu-Hsin Chen | Joel Emer | Vivienne Sze

https://doi.org/10.1109/acssc.2017.8335698 Actions

Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators

PROCEEDINGS ARTICLE published December 2019 in 2019 IEEE International Electron Devices Meeting (IEDM)

Authors: Tien-Ju Yang | Vivienne Sze

https://doi.org/10.1109/iedm19573.2019.8993662 Actions

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

JOURNAL ARTICLE published 2017 in IEEE Micro

Authors: Yu-Hsin Chen | Joel Emer | Vivienne Sze

https://doi.org/10.1109/mm.2017.265085944 Actions

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

JOURNAL ARTICLE published January 2017 in IEEE Journal of Solid-State Circuits

Authors: Yu-Hsin Chen | Tushar Krishna | Joel S. Emer | Vivienne Sze

https://doi.org/10.1109/jssc.2016.2616357 Actions

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

PROCEEDINGS ARTICLE published June 2016 in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)

Authors: Yu-Hsin Chen | Joel Emer | Vivienne Sze

https://doi.org/10.1109/isca.2016.40 Actions
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